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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7046A Phase-locked-loop with lock detector
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
FEATURES * Low power consumption * Centre frequency up to 17 MHz (typ.) at VCC = 4.5 V * Choice of two phase comparators: EXCLUSIVE-OR; edge-triggered JK flip-flop; * Excellent VCO frequency linearity * VCO-inhibit control for ON/OFF keying and for low standby power consumption * Minimal frequency drift * Operation power supply voltage range: VCO section 3.0 to 6.0 V digital section 2.0 to 6.0 V * Zero voltage offset due to op-amp buffering * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT7046 are high-speed Si-gate CMOS devices and are specified in compliance with JEDEC standard no. 7. The 74HC/HCT7046 are phase-locked-loop circuits that comprise a linear voltage-controlled oscillator (VCO) and two different phase comparators (PC1 and PC2) with a common signal input amplifier and a common comparator input. A lock detector is provided and this gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (GND). The value of the CLD capacitor can be determined, using information supplied in Fig.32. The input signal can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input December 1990 amplifiers. With a passive low-pass filter, the "7046" forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques. VCO The VCO requires one external capacitor C1 (between C1A and C1B) and one external resistor R1 (between R1 and GND) or two external resistors R1 and R2 (between R1 and GND, and R2 and GND). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency offset if required. The high input impedance of the VCO simplifies the design of low-pass filters by giving the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEMOUT). In contrast to conventional techniques where the DEMOUT voltage is one threshold voltage lower than the VCO input voltage, here the DEMOUT voltage equals that of the VCO input. If DEMOUT is used, a load resistor (RS) should be connected from DEMOUT to GND; if unused, DEMOUT should be left open. The VCO output (VCOOUT) can be connected directly to the comparator input (COMPIN), or connected via a frequency-divider. The VCO output signal has a duty factor of 50% (maximum expected deviation 1%), if the VCO input is held at a constant DC level. A LOW level at the inhibit input (INH) enables the VCO and demodulator, while a HIGH level turns both off to minimize standby power consumption. The only difference between the HC and HCT versions is the input level specification of the INH input. This input disables the VCO section. The comparators' sections are identical, so that there is no difference in the 2
74HC/HCT7046A
SIGIN (pin 14) or COMPIN (pin 3) inputs between the HC and HCT versions. Phase comparators The signal input (SIGIN) can be directly coupled to the self-biasing amplifier at pin 14, provided that the signal swing is between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.
Phase comparator 1 (PC1)
This is an EXCLUSIVE-OR network. The signal and comparator input frequencies (fi) must have a 50% duty factor to obtain the maximum locking range. The transfer characteristic of PC1, assuming ripple (fr = 2fi) is suppressed, is: V CC V DEMOUT = ---------- ( SIGIN - COMPIN )
where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC1OUT (via low-pass filter). The phase comparator gain is: V CC K p = ---------- ( V r ) . The average output voltage from PC1, fed to the VCO input via the low-pass filter and seen at the demodulator output at pin 10 (VDEMOUT), is the resultant of the phase differences of signals (SIGIN) and the comparator input (COMPIN) as shown in Fig.6. The average of VDEMOUT is equal to 1/2 VCC when there is no signal or noise at SIGIN and with this input the VCO oscillates at the centre frequency (fo). Typical
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
waveforms for the PC1 loop locked at fo are shown in Fig.7. The frequency capture range (2fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out-of-lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With PC1, the capture range depends on the low-pass filter characteristics and can be made as large as the lock range. This configuration retains lock even with very noisy input signals. Typical behaviour of this type of phase comparator is that it can lock to input frequencies close to the harmonics of the VCO centre frequency. The phase comparator gain is: V CC K p = ---------- ( V r ) . 4
74HC/HCT7046A
the low-pass filter. With no signal present at SIGIN the VCO adjusts, via PC2, to its lowest frequency. APPLICATIONS
VDEMOUT is the resultant of the initial phase differences of SIGIN and COMPIN as shown in Fig.8. Typical waveforms for the PC2 loop locked at fo are shown in Fig.9. When the frequencies of SIGIN and COMPIN are equal but the phase of SIGIN leads that of COMPIN, the p-type output driver at PC2OUT is held "ON" for a time corresponding to the phase difference (DEMOUT). When the phase of SIGIN lags that of COMPIN, the n-type driver is held "ON". When the frequency of SIGIN is higher than that of COMPIN, the p-type output driver is held "ON" for most of the input signal cycle time, and for the remainder of the cycle both n and p- type drivers are "OFF" (3-state). If the SIGIN frequency is lower than the COMPIN frequency, then it is the n-type driver that is held "ON" for most of the cycle. Subsequently, the voltage at the capacitor (C2) of the low-pass filter connected to PC2OUT varies until the signal and comparator inputs are equal in both phase and frequency. At this stable point the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at pin 9 is a high impedance. Thus, for PC2, no phase difference exists between SIGIN and COMPIN over the full frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is reduced because both p and n-type drivers are "OFF" for most of the signal input cycle. It should be noted that the PLL lock range for this type of phase comparator is equal to the capture range and is independent of 3
* FM modulation and demodulation * Frequency synthesis and multiplication * Frequency discrimination * Tone decoding * Data synchronization and conditioning * Voltage-to-frequency conversion * Motor-speed control
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. PC2 comprises two D-type flip-flops, control-gating and a 3-state output stage. The circuit functions as an up-down counter (Fig.5) where SIGIN causes an up-count and COMPIN a down-count. The transfer function of PC2, assuming ripple (fr = fi) is suppressed, is: V CC V DEMOUT = ---------- ( SIGIN - COMPIN ) 4
where VDEMOUT is the demodulator output at pin 10; VDEMOUT = VPC2OUT (via low-pass filter).
December 1990
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C;
74HC/HCT7046A
TYPICAL SYMBOL PARAMETER fo CI CPD Notes 1. Applies to the phase comparator section only (VCO disabled). For power dissipation of VCO and demodulator sections see Figs 20, 21 and 22. 2. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". VCO centre frequency input capacitance (pin 5) power dissipation capacitance per package notes 1 and 2 CONDITIONS HC C1 = 40 pF; R1 = 3 k; VCC = 5 V 19 3.5 24 HCT 19 3.5 24 MHz pF pF UNIT
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
PIN DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL LD PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN CLD VCC NAME AND FUNCTION lock detector output (active HIGH) phase comparator 1 output comparator input VCO output inhibit input capacitor C1 connection A capacitor C1 connection B ground (0 V) VCO input demodulator output resistor R1 connection resistor R2 connection phase comparator 2 output signal input lock detector capacitor input positive supply voltage
74HC/HCT7046A
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
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5
December 1990
4 SIG IN 3 14
Philips Semiconductors
C1
6
7
C1A
C1B VCO OUT COMP IN
4046A
identical to 4046A PC1 OUT 2 PHASE COMPARATOR 1 PC2 OUT 13 R3
12 R2
7046A
PHASE COMPARATOR 2 PC2 OUT 13
R2
VCO PHASE COMPARATOR PCP OUT 1 2 R4 C2
11 R1
R1
Phase-locked-loop with lock detector
LOCK DETECTOR LD 1 C LD 15 C CLD
MGA847
6
9
PC3 OUT 15 PHASE COMPARATOR 3
INH
DEM OUT VCO IN
5
10
RS
(a)
(b)
74HC/HCT7046A
Product specification
Fig.4 Functional diagram.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.5 Logic diagram.
Fig.6
Phase comparator 1: average output voltage versus input phase difference: V CC V DEMOUT = V PC1OUT = ---------- ( SIGIN - COMPIN ) DEMOUT = SIGIN - COMPIN
Fig.7
Typical waveforms for PLL using phase comparator 1, loop locked at fo.
December 1990
7
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.8
Phase comparator 2: average output voltage versus input phase difference: V CC V DEMOUT = V PC2OUT = ---------- ( SIGIN - COMPIN ) 4 Fig.9 DEMOUT = ( SIGIN - COMPIN ) . Typical waveforms for PLL using phase comparator 2, loop locked at fo.
December 1990
8
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
RECOMMENDED OPERATING CONDITIONS FOR 74HC/HCT 74HC SYMBOL PARAMETER min. VCC VCC VI VO Tamb Tamb tr, tf DC supply voltage DC supply voltage if VCO section is not used DC input voltage range DC output voltage range 3.0 2.0 0 0 typ. 5.0 5.0 max. min. 6.0 6.0 VCC VCC +85 +125 1000 500 400 4.5 4.5 0 0 -40 -40 typ. 5.0 5.0 74HCT
74HC/HCT7046A
UNIT max. 5.5 5.5 VCC VCC +85 +125 V V V V C C
CONDITIONS
operating ambient temperature range -40 operating ambient temperature range -40 input rise and fall times (pin 5) 6.0
see DC and AC CHARACTERISTICS
6.0
500
ns
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL VCC IIK IOK IO ICC; IGND Tstg Ptot PARAMETER DC supply voltage DC input diode current DC output diode current DC output source or sink current DC VCC or GND current storage temperature range power dissipation per package plastic DIL plastic mini-pack (SO) 750 500 mW mW -65 MIN. -0.5 MAX. +7 20 20 25 50 +150 UNIT V mA mA mA mA C for temperature range: -40 to +125 C 74HC/HCT above +70 C: derate linearly with 12 mW/K above +70 C: derate linearly with 8 mW/K for VI < -0.5 V or VI > VCC + 0.5 V for VO < -0.5 V or VO > VCC + 0.5 V for - 0.5 V < VO < VCC + 0.5 V CONDITIONS
December 1990
9
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
DC CHARACTERISTICS FOR 74HC Quiescent supply current Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER min. ICC quiescent supply current (VCO disabled) +25 -40 to +85 -40 to +125 max. 160.0 A
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) 6.0
OTHER
typ. max. min. max. min. 8.0 80.0
pins 3, 5, and 14 at VCC; pin 9 at GND; II at pins 3 and 14 to be excluded
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10
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
Phase comparator section Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER min. VIH DC coupled HIGH level input voltage SIGIN, COMPIN DC coupled LOW level input voltage SIGIN, COMPIN
HIGH level output voltage LD, PCnOUT HIGH level output voltage LD, PCnOUT
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 3.0 4.5 6.0 6.0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL
VCC
+25
-40 to +85
-40 to +125
VI
OTHER
typ. max. min. max. min. max. 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 4.0 9.0 23.0 38.0 5.0 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 5.0 11.0 27.0 45.0 10.0 1.5 3.15 4.2 0.5 1.35 1.8 V
1.5 3.15 4.2
VIL
V
VOH
1.9 4.4 5.9 3.98 5.48
2.0 4.5 6.0 4.32 5.81 0 0 0
V
-IO = 20 A -IO = 20 A -IO = 20 A
-IO = 4.0 mA -IO = 5.2 mA
VOH
V
VOL
LOW level output voltage LD, PCnOUT LOW level output voltage LD, PCnOUT input leakage current SIGIN, COMPIN
V
IO = 20 A IO = 20 A IO = 20 A
IO = 4.0 mA IO = 5.2 mA
VOL II
0.15 0.26 0.16 0.26 3.0 7.0 18.0 30.0 0.5
V A
or
GND
IOZ
3-state OFF-state current PC2OUT input resistance SIGIN, COMPIN 800 250 150
A
VIH or VIL
VO = VCC or GND
RI
k
3.0 4.5 6.0
VI at self-bias operating point; VI = 0.5 V; see Figs 10, 11 and 12
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
VCO section Voltages are referenced to GND (ground = 0 V) Tamb (C) SYMBOL 74HC PARAMETER min. VIH HIGH level input voltage INH LOW level input voltage INH
HIGH level
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 3.0 4.5 6.0 4.5 6.0 4.5 6.0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL
VCC
+25
-40 to +85
-40 to +125 min. 2.1 3.15 4.2 max.
VI
OTHER
typ. max. min. max. 1.7 2.4 3.2 1.3 2.1 2.8 0.9 1.35 1.8 2.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.1 0.1 0.1 0.33 0.33 0.47 0.47 2.1 3.15 4.2 0.9 1.35 1.8
2.1 3.15 4.2
V 0.9 1.35 1.8
VIL
V
VOH
output voltage VCOOUT
HIGH level
2.9 4.4 5.9 3.98 5.48
3.0 4.5 6.0 4.32 5.81 0 0 0
2.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.54 0.54
V
-IO = 20 A -IO = 20 A -IO = 20 A -IO = 4.0 mA -IO = 5.2 mA IO = 20 A IO = 20 A IO = 20 A IO = 4.0 mA IO = 5.2 mA IO = 4.0 mA IO = 5.2 mA
VOH
output voltage VCOOUT LOW level output voltage VCOOUT LOW level output voltage VCOOUT LOW level output voltage C1A, C1B (test purposes only) input leakage current INH, VCOIN resistor range
V
VOL
V
VOL
0.15 0.26 0.16 0.26 0.40 0.40
V
VOL
V
II
0.1 3.0 3.0 3.0 3.0 3.0 3.0 40 40 40 1.1 1.1 1.1 300 300 300 300 300 300 no limit 1.9 3.4 4.9
1.0
1.0
A
6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0
or
GND
R1
k
note 1
R2
resistor range
k
note 1
C1
capacitor range
pF
VVCOIN
operating voltage range at VCOIN
V
over the range specified for R1; for linearity see Figs 18 and 19.
Note 1. The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/or R2 are/is > 10 k. December 1990 12
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
Demodulator section Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HC SYMBOL PARAMETER min. RS resistor range 50 50 50 +25 typ. -40 to +85 -40 to +125 max.
74HC/HCT7046A
TEST CONDITIONS UNIT VCC (V) 3.0 4.5 6.0
OTHER at RS > 300 k the leakage current can influence VDEMOUT VI = VVCOIN = 1/2 VCC; values taken over RS range; see Fig.13 VDEMOUT = 1/2 VCC
max. min. max. min. 300 300 300
k
VOFF
offset voltage VCOIN to VDEMOUT
30 20 10
mV
3.0 4.5 6.0
RD
dynamic output resistance at DEMOUT
25 25 25
3.0 4.5 6.0
December 1990
13
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
AC CHARACTERISTICS FOR 74HC Phase comparator section GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay SIGIN, COMPIN to PC1OUT 3-state output enable time SIGIN, COMPIN to PC2OUT 3-state output disable time SIGIN, COMPIN to PC2OUT output transition time +25 typ. 58 21 17 74 27 22 96 35 28 19 7 6 9 11 15 33 -40 to +85 -40 to +125
74HC/HCT7046A
TEST CONDITIONS UNIT VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 3.0 4.5 6.0
OTHER
max. min. max. min. max. 200 40 34 280 56 48 325 65 55 75 15 13 250 50 43 350 70 60 405 81 69 95 19 16 300 60 51 420 84 71 490 98 83 110 22 19 ns Fig.14
tPZH/ tPZL
ns
Fig.15
tPHZ/ tPLZ
ns
Fig.15
tTHL/ tTLH
ns
Fig.14
VI(p-p)
AC coupled input sensitivity (peak-to-peak value) at SIGIN or COMPIN
mV
fi = 1 MHz
VCO section GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. f/T frequency stability with temperature change VCO centre 7.0 10.0 frequency 11.0 17.0 (duty factor = 50%) 13.0 21.0
VCO frequency
TEST CONDITIONS
-40 to +85 max. typ. 0.20 0.15 0.14
-40 to +125
UNIT V CC (V)
OTHER
typ.
max. min. max. %/K 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 3.0 4.5 6.0 VI = VVCOIN =1/2 VCC ; R1 = 100 k; R2 = ; C1 = 100 pF; see Fig.16 VVCOIN = 1/2 VCC; R1 = 3 k; R2 = ; C1 = 40 pF; see Fig.17 R1 = 100 k; R2 = ; C1 = 100 pF; see Figs 18 and 19
fo
MHz
fVCO
linearity VCO duty factor at VCOOUT
1.0 0.4 0.3 50 50 50
%
%
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
DC CHARACTERISTICS FOR 74HCT Quiescent supply current Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER min. ICC quiescent supply current (VCO disabled) +25 -40 to +85 -40 to +125
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) 6.0
OTHER
typ. max. min. max. min. max. 8.0 80.0 160.0 A pins 3, 5 and 14 at VCC; pin 9 at GND; II at pins 3 and 14 to be excluded pins 3 and 14 at VCC; pin 9 at GND; II at pins 3 and 14 to be excluded
ICC
additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) VI = VCC - 2.1 V
100
360
450
490
A
4.5 to 5.5
Note 1. The value of additional quiescent supply current (ICC) for a unit load of 1 is given above. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT INH
UNIT LOAD COEFFICIENT 1.00
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
Phase comparator section Voltages are referenced to GND (ground = 0 V) Tamb (C) SYM BOL 74HCT PARAMETER +25 min. typ. VIH DC coupled HIGH level input voltage 3.15 2.4 SIGIN, COMPIN DC coupled LOW level input voltage SIGIN, COMPIN
HIGH level output voltage
74HC/HCT7046A
TEST CONDITIONS UNIT VCC (V) VI
-40 to +85
-40 to +125 max.
OTHER
max min. max. min.
V
4.5
VIL
2.1
1.35
V
4.5 VIH or VIL VIH or VIL VIH or VIL VIH or VIL
VCC
VOH
LD, PCnOUT
HIGH level output voltage
4.4
4.5
4.4
4.4
V
4.5
-IO = 20 A
VOH
LD, PCnOUT LOW level output voltage LD, PCnOUT LOW level output voltage LD, PCnOUT input leakage current SIGIN, COMPIN 3-state OFF-state current PC2OUT input resistance SIGIN, COMPIN
3.98 4.32
3.84
3.7
V
4.5
-IO = 4.0 mA
VOL
0
0.1
0.1
0.1
V
4.5
IO = 20 A
VOL
0.15 0.26
0.33
0.4
V
4.5
IO = 4.0 mA
II
30
38
45
A
5.5
or
GND
IOZ
0.5
5.0
10.0
A
5.5
VIH or VIL
VO = VCC or GND
RI
250
k
4.5
VI at self-bias operating point; VI = 0.5 V; see Figs 10, 11 and 12
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
DC CHARACTERISTICS FOR 74HCT VCO section Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER +25 -40 to +85 -40 to +125 max. V
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) 4.5 to 5.5 4.5 to 5.5 4.5 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIH or VIL
VCC
VI
OTHER
min. typ. max. min. max. min. VIH HIGH level input voltage INH LOW level input voltage INH
HIGH level output voltage VCOOUT HIGH level output voltage VCOOUT
2.0
1.6
2.0
2.0
VIL
1.2
0.8
0.8
0.8
V
VOH
4.4
4.5
4.4
4.4
V
-IO = 20 A
VOH
3.98
4.32
3.84
3.7
V
4.5
-IO = 4.0 mA
VOL
LOW level output voltage VCOOUT LOW level output voltage VCOOUT LOW level output voltage C1A, C1B (test purposes only) input leakage current INH, VCOIN resistor range resistor range capacitor range operating voltage range at VCOIN 3.0 3.0 40 1.1
0
0.1
0.1
0.1
V
4.5
IO = 20 A
VOL
0.15 0.26
0.33
0.4
V
4.5
IO = 4.0 mA
VOL
0.40
0.47
0.54
V
4.5
IO = 4.0 mA
II
0.1
1.0
1.0
A
5.5
or
GND
R1 R2 C1 VVCOIN
300 300 no limit 3.4
k k pF V
4.5 4.5 4.5 4.5
note 1 note 1
over the range specified for R1; for linearity see Figs 18 and 19.
Note 1. The parallel value of R1 and R2 should be more than 2.7 k. Optimum performance is achieved when R1 and/or R2 are/is > 10 k.
December 1990
17
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
Demodulator section Voltages are referenced to GND (ground = 0 V) Tamb (C) 74HCT SYMBOL PARAMETER min. RS resistor range 50 +25 -40 to +85
-40 to +125
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) k 4.5
OTHER at RS > 300 k the leakage current can influence VDEMOUT VI = VVCOIN = 1/2 VCC; values taken over RS range; see Fig.13 VDEMOUT = 1/2 VCC
typ. max. min. max. min. max. 300
VOFF
offset voltage VCOIN to VDEMOUT
20
mV
4.5
RD
dynamic output
25
4.5
resistance at DEMOUT AC CHARACTERISTICS FOR 74HCT Phase comparator section GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay SIGIN, COMPIN to PC1OUT 3-state output enable time SIGIN, COMPIN to PC2OUT 3-state output disable time SIGIN, COMPIN to PC2OUT output transition time AC coupled input sensitivity (peak-to-peak value) at SIGIN or COMPIN 21 max. 40 74HCT -40 to +85 min. max. 50 -40 to +125 min. max. 60 ns 4.5 Fig.14 UNIT VCC (V) OTHER TEST CONDITIONS
tPZH/ tPZL
27
56
70
84
ns
4.5
Fig.15
tPHZ/ tPLZ
35
65
81
98
ns
4.5
Fig.15
tTHL/ tTLH VI(p-p)
7 15
15
19
22
ns mV
4.5 4.5
Fig.14 fi = 1 MHz
December 1990
18
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
VCO section GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. f/T frequency stability with temperature change max. -40 to +85 typ. 0.15 -40 to +125
74HC/HCT7046A
TEST CONDITIONS UNIT V CC (V) %/K 4.5
OTHER
max. min. max. VI = VCOIN within recommended range; R1 = 100 k; R2 = ; C1 = 100 pf; see Fig.16b VVCOIN = 1/2 VCC; R1 = 3 k; R2 = ; C1 = 40 pF; see Fig.17 R1 = 100 k; R2 = ; C1 = 100 pF; see Figs 18 and 19
fo
VCO centre frequency 11.0 (duty factor = 50%)
17.0
MHz
4.5
fVCO
VCO frequency
0.4
%
4.5
linearity
VCO
duty factor at VCOOUT
50
%
4.5
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
FIGURE REFERENCES FOR DC CHARACTERISTICS
74HC/HCT7046A
Fig.10 Typical input resistance curve at SIGIN, COMPIN.
Fig.11 Input resistance at SIGIN, COMPIN with VI = 0.5 V at self-bias point.
____ RS = 50 k - - - - RS = 300 k
Fig.12 Input current at SIGIN, COMPIN with VI = 0.5 V at self-bias point.
Fig.13 Offset voltage at demodulator output as a function of VCOIN and RS.
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
AC WAVEFORMS
74HC/HCT7046A
(1) HC : VM = 50%; VI = GND to VCC.
Fig.14 Waveforms showing input (SIGIN, COMPIN) to output (PC1OUT) propagation delays and the output transition times.
(1) HC : VM = 50%; VI = GND to VCC.
Fig.15 Waveforms showing the 3-state enable and disable times for PC2OUT.
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December 1990 22
Philips Semiconductors
Phase-locked-loop with lock detector
handbook, halfpage
f (%)
25
MSB710
MSB711
MSB712
handbook, halfpage
25
f (%)
handbook, halfpage
25
f (%)
VCC = 3V 3V 5V 6V
20
20
20
5V 6V
15
VCC =
6V 5V
15 3V 5V 10 3V 6V
VCC = 3V A 5V 6V
15
10
10
5
3V 4.5 V 5V 6V
5
5
0
0
0
-5
5
5
-10
10
10
-15
15
15
-20
20
20
-25 -50
0
50
100 150 Tamb (oC)
25
50
0
50
100 150 Tamb ( o C)
25
50
0
50
100 150 Tamb ( o C)
(a)
(b)
(c)
74HC/HCT7046A
Product specification
Fig.16 Frequency stability of the VCO as a function of ambient temperature with supply voltage as a parameter. without offset (R2 = ): (a) R1 = 3 k; (b) R1 = 10 k; (c) R1 = 300 k. - - - - with offset (R1 = ): (a) R2 = 3 k; (b) R2 = 10 k; (c) R2 = 300 k. In (b), the frequency stability for R1 = R2 = 10 k at 5 V is also given (curve A). This curve is set by the total VCO bias current, and is not simply the addition of the two 10 k stability curves. C1 = 100 pF; VVCO IN = 0.5 VCC.
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
AC WAVEFORMS
74HC/HCT7046A
To obtain optimum temperature stability, C1 must be a small as possible, but larger than 100 pF.
Fig.16 Continued.
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.17 Graphs showing VCO frequency (fVCO) as a function of the VCO input voltage (VVCOIN).
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.18 Definition of VCO frequency linearity: V = 0.5 V over the VCC range: for VCO linearity f1 + f2 f 0 = -------------2 f 0 - f 0 linearity = --------------- x 100 % f 0 Fig.19 Frequency linearity as a function of R1, C1 and VCC: R2 = and V = 0.5 V.
December 1990
25
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
____ C1 = 40 pF - - - - C1 = 1 F
____ C1 = 40 pF - - - - C1 = 1 F
Fig.20 Power dissipation versus the value of R1: CL = 50 pF; R2 = ; VVCOIN = 1/2 VCC; Tamb = 25 C.
Fig.21 Power dissipation versus the value of R2: CL = 50 pF; R1 = ; VVCOIN = GND = 0 V; Tamb = 25 C.
Fig.22 Typical dc power dissipation of demodulator section as a function of RS: R1 = R2 = ; Tamb = 25 C; VVCOIN = 1/2 VCC.
December 1990
26
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
APPLICATION INFORMATION
74HC/HCT7046A
This information is a guide for the approximation of values of external components to be used with the 74HC/HCT7046 in a phase-lock-loop system. References should be made to Figs 27, 28 and 29 as indicated in the table. Values of the selected components should be within the following ranges: R1 R2 R1 + R2 C1 between 3 k and 300 k; between 3 k and 300 k; parallel value > 2.7 k; greater than 40 pF.
SUBJECT
PHASE COMPARATOR
DESIGN CONSIDERATIONS VCO frequency characteristic
VCO frequency without extra offset
PC1, PC2
With R2 = and R1 within the range 3 k < R1 < 300 k, the characteristics of the VCO operation will be as shown in Fig. 23. (Due to R1, C1 time constant a small offset remains when R2 = .)
Fig. 23 Frequency characteristic of VCO operating without offset: fo = centre frequency; 2fL = frequency lock range. Selection of R1 and C1 PC1 PC2 Given fo, determine the values of R1 and C1 using Fig.27. Given fmax and fo, determine the values of R1 and C1 using Fig.27, use Fig.29 to obtain 2fL and then use this to calculate fmin.
December 1990
27
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
SUBJECT
PHASE COMPARATOR
DESIGN CONSIDERATIONS VCO frequency characteristic
VCO frequency with extra offset
PC1, PC2
With R1 and R2 within the ranges 3 k < R1 < 300 k, 3 k < R2 < 300 k, the characteristics of the VCO operation will be as shown in Fig. 24.
Fig. 24 Frequency characteristic of VCO operating with offset: fo = centre frequency; 2fL = frequency lock range. Selection of R1, R2 and C1 PC1, PC2 Given f0 and fL, determine the value of product R1C1 by using Fig.29. Calculate foff from the equation foff = fo - 1.6fL. Obtain the values of C1 and R2 by using Fig.28. Calculate the value of R1 from the value of C1 and the product R1C1.
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
SUBJECT PLL conditions with no signal at the SIGIN input PLL frequency capture range
PHASE COMPARATOR PC1 PC2 PC1, PC2
DESIGN CONSIDERATIONS VCO adjusts to fo with DEMOUT = 90 and VVCOIN = 1/2 VCC (see Fig.6). VCO adjusts to fo with DEMOUT = -360 and VVCOIN = min. (see Fig.8). Loop filter component selection
(a) = R3 x C2
(b) amplitude characteristic
(c) pole-zero diagram
Fig. 25 Simple loop filter for PLL without offset; R3 500 .
(a) 1 = R3 x C2; (b) amplitude characteristic 2 = R4 x C2; 3 = (R3 + R4) x C2 PLL locks on PC1 harmonics at centre frequency PC2 noise rejection at signal input PC1 PC2 yes no high low fr = 2fi, large ripple content at DEMOUT = 90 fr = fi, small ripple content at DEMOUT = 0
(c) pole-zero diagram
Fig. 26 Simple loop filter for PLL with offset; R3 + R4 500 .
AC ripple content PC1 when PLL is PC2 locked
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF. (2) Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce almost the same VCO output frequency.
Fig.27 Typical value of VCO centre frequency (fo) as a function of C1: R2 = ; VVCOIN = 1/2 VCC; INH = GND; Tamb = 25 C.
December 1990
30
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
APPLICATION INFORMATION
74HC/HCT7046A
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF. (2) Interpolation for various values of R2 can be easily calculated because a constant R2C2 product will produce almost the same VCO output frequency.
Fig.28 Typical value of frequency offset as a function of C1: R1 = ; VVCOIN = 1/2 VCC; INH = GND; Tamb = 25 C.
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.29 Typical frequency lock range (2fL) versus the product R1C1: VVCOIN range = 0.9 to (VCC - 0.9) V; R2 = ; VCO gain: 2f L K V = ------------------------------------ 2 (r/s/V). V VCOIN range
December 1990
32
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
APPLICATION INFORMATION Lock-detection circuit The built-in lock-detection circuit will only work when used in conjunction with the phase comparator PC2. The lock-indication is derived from the phase error between SIGIN and COMPIN. The PC2 has a typical phase error of zero degrees over the entire VCO operating range. However, to remain in-lock the circuit requires some small adjustments. The variation is dependent on the loop parameters and back-lash time (typically 5 ns). Depending
74HC/HCT7046A
on the application, the phase error can be defined as the limit, a phase error of greater magnitude would be considered out-of-lock. An example of an in-lock detection circuit using the "7046A" is shown in Fig.30. If the PLL is in-lock, only very small pulses will come from the "up" or "down" connections of PC2. These pulses are filtered out by a RC network. A Schmitt trigger produces a steady state level, a HIGH level indicates an in-lock condition and a pulsed output indicates an out-of-lock condition as shown in Fig.31.
See Fig.31 for input waveform.
Fig.30 An example of an in-lock detection circuit using the "7046A".
(a)
(b)
Fig.31 Waveforms showing the lock detection process; (a) in-lock; (b) out-of-lock.
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
CLD tLD
= =
capacitor connected to pin 15 (includes the parasitic input capacitance of the IC, approximately 3.5 pF). phase difference between SIGIN and COMPIN (positive-going edges).
Fig.32 CLD capacitor value versus typical tLD.
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
The maximum permitted phase error must be defined, before tLD can be defined using the following formula: max 1 t LD = ----------- x ----- . 360 f IN
74HC/HCT7046A
Using this calculated value in Fig.32, it is possible to define the value of CLD, e.g. assuming the phase error is 36 and fIN = 2 MHz: 36 1 t LD = --------- x ----------------- = 50 ns, 360 2 MHz
and using Fig.32, it can be seen that CLD is 26 pF. With the addition of one retriggerable monostable (e.g. "123", "423" or "4538") a steady state LOW and HIGH indication can be obtained, as shown in Fig.33. Fig.33 Steady state signal for lock indication.
December 1990
35
Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
PLL design example The frequency synthesizer, used in the design example shown in Fig.34, has the following parameters: Output frequency: 2 MHz to 3 MHz frequency steps : 100 kHz settling time : 1 ms overshoot : < 20% The open-loop gain is H (s) x G (s) = Kp x Kf x Ko x Kn. Where: Kp Kf Ko Kn = = = = phase comparator gain low-pass filter transfer gain Kv/s VCO gain 1/n divider ratio
74HC/HCT7046A
The characteristics equation is: 1 + H (s) x G (s) = 0. This results in: Kp x Kv x Kn 2 1 + Kp x Kv x Kn x 2 s + ----------------------------------------------------- s + ------------------------------- = 0. ( 1 + 2) ( 1 + 2) The natural frequency n is defined as follows: Kp x Kv x Kn n = ------------------------------- . ( 1 + 2) and the damping value is defined as follows: 1 + Kp x Kv x Kn x 2 1 = --------- x ----------------------------------------------------- . 2 n 1 + 2 The overshoot and settling time percentages are now used to determine n. From Fig.35 it can be seen that the damping ratio = 0.8 will produce an overshoot of less than 20% and settle to within 5% at nt = 4.5. The required settling time is 1 ms. This results in: 3 5 5 n = -- = -------------- = 5 x 10 r/s. t 0.001 Rewriting the equation for natural frequency results in: Kp x Kv x Kn ( 1 + 2 ) = ------------------------------- . 2 n The maximum overshoot occurs at Nmax.: 0.4 x 2 x 10 ( 1 + 2 ) = -------------------------------- = 0.0011 s. 2 5000 x 30 When C2 = 470 nF, then ( 1 + 2) x 2 x n x - 1 R4 = ---------------------------------------------------------------- = 790 . Kp x Kv x Kn R3 is calculated using the damping ratio equation: 1 R3 = ------- - R4 = 2 k. C2
6
The programmable counter ratio Kn can be found as follows: f out 2 MHz N min. = ---------- = --------------------- = 20 f step 100 kHz f out 3 MHz N max. = ---------- = --------------------- = 30 f step 100 kHz The VCO is set by the values of R1, R2 and C1, R2 = 10 k (adjustable). The values can be determined using the information in the section "DESIGN CONSIDERATIONS". With fo = 2.5 MHz and fL = 500 kHz this gives the following values (VCC = 5.0 V): R1 = 10 k R2 = 10 k C1 = 500 pF The VCO gain is: 2f L x 2 x 6 1 MHz K V = --------------------------------------------- = = ----------------- x 2 2 x 10 r/s/v 3.2 0.9 - ( V CC - 0.9 ) The gain of the phase comparator is: V CC K p = ------------ = 0.4 V/r. 4x The transfer gain of the filter is given by: 1 + 2 s K f = -----------------------------------1 + ( 1 + 2) s Where: 1 = R3C2 and 2 = R4C2.
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.34 Frequency synthesizer.
Note For an extensive description and application example please refer to application note ordering number 9398 649 90011. Also available a computer design program for PLL's ordering number 9398 961 10061.
1.6
MGA959
-0.6 -0.4 -0.2
e (t) e / n
1.4
= 0.3
0.5 0.707 1.0
e (t) e / n
1.2
= 5.0
1.0
= 2.0
0
0.8
0.2
0.6 0.4
0.4 0.6
0.2
0.8
0
0
1
2
3
4
5
6
7
nt
8
1.0
Fig.35 Type 1, second order frequency step response.
Since the output frequency is proportional to the VCO control voltage, the PLL frequency response can be observed with an oscilloscope by monitoring pin 9 of the VCO. The average frequency response, as calculated by the Laplace method, is found experimentally by smoothing this voltage at pin 9 with a simple RC filter, whose time constant is long compared to the phase detector sampling rate but short compared to the PLL response time.
December 1990
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Philips Semiconductors
Product specification
Phase-locked-loop with lock detector
74HC/HCT7046A
Fig.36 Frequency compared to the time response.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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